// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II 64-Bit Version 13.0 (Build Build 232 06/12/2013)
// Created on Sat May 14 19:47:18 2016

NiosIITemplate NiosIITemplate_inst
(
	.clk_1khz(clk_1khz_sig) ,	// output  clk_1khz_sig
	.clk(clk_sig) ,	// input  clk_sig
	.rst_n(rst_n_sig) ,	// input  rst_n_sig
	.S1(S1_sig) ,	// input  S1_sig
	.S2(S2_sig) ,	// input  S2_sig
	.S3(S3_sig) ,	// input  S3_sig
	.S4(S4_sig) ,	// input  S4_sig
	.LED(LED_sig) ,	// output [3:0] LED_sig
	.SW1(SW1_sig) ,	// input  SW1_sig
	.SW2(SW2_sig) ,	// input  SW2_sig
	.KEY_H(KEY_H_sig) ,	// inout [3:0] KEY_H_sig
	.KEY_L(KEY_L_sig) ,	// inout [3:0] KEY_L_sig
	.sdram_wire_addr(sdram_wire_addr_sig) ,	// output [11:0] sdram_wire_addr_sig
	.sdram_wire_ba(sdram_wire_ba_sig) ,	// output [1:0] sdram_wire_ba_sig
	.sdram_wire_cas_n(sdram_wire_cas_n_sig) ,	// output  sdram_wire_cas_n_sig
	.sdram_wire_cke(sdram_wire_cke_sig) ,	// output  sdram_wire_cke_sig
	.sdram_wire_cs_n(sdram_wire_cs_n_sig) ,	// output  sdram_wire_cs_n_sig
	.sdram_wire_dq(sdram_wire_dq_sig) ,	// inout [15:0] sdram_wire_dq_sig
	.sdram_wire_dqm(sdram_wire_dqm_sig) ,	// output [1:0] sdram_wire_dqm_sig
	.sdram_wire_ras_n(sdram_wire_ras_n_sig) ,	// output  sdram_wire_ras_n_sig
	.sdram_wire_we_n(sdram_wire_we_n_sig) ,	// output  sdram_wire_we_n_sig
	.SDRAMclk(SDRAMclk_sig) ,	// output  SDRAMclk_sig
	.epcs_data(epcs_data_sig) ,	// input  epcs_data_sig
	.epcs_sdo(epcs_sdo_sig) ,	// output  epcs_sdo_sig
	.epcs_dclk(epcs_dclk_sig) ,	// output  epcs_dclk_sig
	.epcs_sce(epcs_sce_sig) ,	// output  epcs_sce_sig
	.pwm_out(pwm_out_sig) ,	// output  pwm_out_sig
	.sig_in(sig_in_sig) ,	// input  sig_in_sig
	.lcdcs(lcdcs_sig) ,	// output  lcdcs_sig
	.lcdrst(lcdrst_sig) ,	// output  lcdrst_sig
	.lcdrs(lcdrs_sig) ,	// output  lcdrs_sig
	.lcdspi_mosi(lcdspi_mosi_sig) ,	// output  lcdspi_mosi_sig
	.lcdspi_sclk(lcdspi_sclk_sig) ,	// output  lcdspi_sclk_sig
	.lcdleda(lcdleda_sig) ,	// output  lcdleda_sig
	.fcclk(fcclk_sig) ,	// output  fcclk_sig
	.date_sin(date_sin_sig) 	// output [13:0] date_sin_sig
);

